1. Field of the Invention
The present invention relates to a multiprocessor system including a plurality of processors, and, more particularly, to a multiprocessor system, a shared-memory controlling method, a recording medium and a data signal embedded in a carrier wave, for efficiently controlling access to a shared memory by each of the plurality of processors.
2. Description of the Related Art
Conventionally, there are proposed various methods for controlling access to a shared memory in a multiprocessor. For example, Unexamined Japanese Patent Application KOKAI Publication No. H4-291085 discloses a memory accessing technique to be employed in multiprocessor systems.
According to the technique disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H4-291085, a 2-port memory serving as a shared memory and an access-flag area setting the access rights to the shared memory are set on each CPU included in the multiprocessor system. In the multiprocessor system, only one CPU having successfully set an access flag in the access flag area is permitted to access the 2-port memory, so as to reliably realize the access to the shared memory.
Additionally, Unexamined Japanese Patent Application KOKAI Publication No.
H3-054660 discloses a technique regarding a shared-memory management technique to be employed in multiprocessor systems.
In the system disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H3-054660, there are included a priority control circuit which has exclusive control over CPUs and a bus-gate circuit which controls the access to the shared memory by the CPUs. Any of those CPUs which intends to access the shared memory sends a request signal to the priority control circuit. Upon this, the priority control circuit exercises the exclusive control over the CPUs, in accordance with the request signal sent from each of the CPUs, and sends a response signal to either one of the CPUs. After this, the priority control circuit controls a bus gate circuit, and sets the CPU to which the response signal is sent and the shared memory into a state where they can be accessed.
Hence, the multiprocessor system can access the shared memory while preventing to lower the system performance of the multiprocessor system.
The multiprocessor system of this invention, however, has the following problems.
In the conventional multiprocessor system, a recovery process for recovering the failure in updating data in the shared memory and a confirmation process for confirming whether data is updated in the shared memory cannot be carried out in cooperation with each of the processors.
A non-volatile memory, such as a Flash Memory, etc. is employed as the shared memory of the multiprocessor system. Since the flash memory is expensive to buy, many flash memories can not be prepared. In this structure, it is preferred that the data handled by each of the processors be efficiently and centrally managed in the multiprocessor system.
For example, in a multiprocessor system which handles a large volume of service data (e.g. data representing voices, picture images, motion images, etc.) which can be downloaded from an external host computer, it is desired that each of processors efficiently stores and updates the service data in the shared memory in cooperation with each other.
In addition, in the conventional multiprocessor system, the processors can individually be reset.